Technical Field
The present invention relates to a fabricating process for package substrate; especially relates to a warpage reduction fabricating process for package substrate.
Description of Related Art
Since semiconductor package technology has developed toward thinner package substrate with higher circuitry density. However, warpage reduction management is one of the critical issues for package substrate due to mismatch of Coefficient of Thermal Expansion (CTE) among different material layers processed during fabricating.
FIG. 1 shows a prior art
FIG. 1 shows a prior art
FIG. 1 shows a prior art US20150135527A1 which disclosed a fabricating process for package substrate, comprising the following steps:
FIG. 1A shows: preparing a core substrate 10.
FIG. 1B shows: filling metal in each hole to form a plurality of holes 11 from top of the core substrate 10; where a depth of the hole 11 is smaller than a thickness of the core substrate 10.
FIG. 1C shows: filling metal in the holes 11 to form a plurality of metal pillars 12 in the core substrate 10.
FIG. 1D shows: forming a redistribution layer RDL on a top surface of the metal pillars 12. The redistribution layer RDL has a redistribution circuitry 14 embedded in dielectric layer 13. The redistribution circuitry 14 has a plurality of top metal pad 141 and a bottom metal pad 142. Each top of the metal pillars 12 is electrically coupled to a bottom surface of a corresponding bottom metal pad 142.
FIG. 1E shows: thinning from bottom of the core substrate 10 to expose a bottom surface of each metal pillar 12.
The prior art disclosed a fabricating process including a redistribution layer RDL that is formed after metal pillars 12 are formed.